1. Field of the Invention
The present invention generally relates to the field of integrated circuit technology, and more specifically the invention relates to a method in the fabrication of a monolithically integrated vertical device on an SOI (silicon-on-insulator) substrate.
2. Description of the Related Art
CMOS SOI technology, especially using thin silicon top layers to allow them to be partially depleted (PD) or fully depleted (FD) already at very low bias voltages, is believed to become a key contributor to the continued increase of circuit performance. The thin silicon top layers have a thickness of less than about 200 nm.
All main IC manufacturers today are evaluating CMOS-SOI for process generations capable of producing features of sizes less than 100 nm. Some of these manufacturers focus their production on PD SOI using commercially available SOI wafers, and all of them are evaluating the potential of FD SOI for low-power digital, mixed and RF applications. SOI technology today is mainly applied in the field of high-speed processor technology. Processors are now produced based on 90 nm CMOS PD SOI with speeds up to 2.5 GHz, corresponding to a speed gain of about 20-25%.
It is well known how to modify CMOS devices for PD or FD SOI. However, to adopt an RF BiCMOS process for PD or FD SOI is a much more complex task since there is no simple way of forming bipolar devices in the thin SOI silicon top layer with similar performance as when vertical NPN transistors are formed in a bulk material.
There are two known main approaches for integrating bipolar devices into a CMOS SOI process.
According to the first main approach no modifications of the SOI starting material are made. Instead, the device is formed in the existing material, see e.g. U.S. Pat. No. 5,087,580 to Eklund. The concept is, however, not possible to extend to thin silicon top layers, such as those needed by modern high-performance SOI processes. Tsaur et al., p. 812 in IEDM Tech. Dig. 1984 disclose the use of a very thick starting top silicon layer, which is made thinner where the MOS devices are to be formed. J. Cai et al., Vertical SiGe-Base Bipolar Transistors on CMOS-Compatible SOI Substrate, p. 215 in Proceedings of the 2003 Bipolar/BiCMOS Circuits and Technology Meeting, disclose an epitaxial-base transistor structure to gain some margin in the thickness requirements, and the thin silicon top layer of the starting material is entirely used for the collector of the bipolar transistor.
According to the second main approach the buried SOI substrate oxide is removed locally, at which areas local bulk regions are formed. Tsaur et al. show in the above paper (FIG. 1b) also this approach, using selective epitaxial growth (SEG) to create the islands for the bipolar devices. In U.S. Pat. No. 4,575,925 to Kanbara et al. methods to create isolated, rather deep, silicon “islands”, which are used to form conventional diffused bipolar transistors, are disclosed. U.S. Pat. Nos. 5,904,535 and 6,232,649 to Lee show structures and methods similar to those disclosed by Tsaur et al., but which are modified to modern substrate and process technology, and which are extended to include oxide spacers at the edge of the bulk islands in order to improve the device isolation. Terada et al., IEEE Transactions on Electron Devices, p. 2052, September 1990, and Burghartz et al. in IEEE Transactions on Electron Devices, p. 1379, August 1994 Selective epitaxial growth (SEG) disclose the formation of rather complex isolated structures using selective epitaxial growth (SEG). Additional lateral extensions are created by severe SEG overgrowth and additional polycrystalline silicon deposition, and the planarization is achieved by polishing.
The device structures must be able to scale to very thin silicon layer thickness, therefore only the second main approach can be considered as viable. The technique using a very thick starting top silicon layer, which is made thinner where the MOS devices are to be formed as disclosed by Tsaur et al. requires high quality silicon etch to make the silicon layer thinner in the regions used for MOS devices. When the layer thickness is made very thin this approach is not preferred because of the precision and variation over the wafer in silicon etch rate.
The second approach disclosed by Tsaur et al. lacks isolation of the buried collector “islands”. Also, the difference in height between CMOS areas and bipolar areas may create e.g. focusing problems during the lithography steps, or need for large planarization before the metallization.
The methods described by Kanbara are quite complicated and the dimensions are not fitted to permit integration of the silicon “islands” with thin silicon SOI.
U.S. Pat. Nos. 5,904,535 and 6,232,649 disclose structures and methods which are far from optimal with regards to the complicated formation of the spacers used for the device isolation. Furthermore, the spacers create large walls, or steps, at the surface around the silicon islands, which requires good planarization for the interconnections between the bipolar transistors and the rest of the circuit.